Altera® Stratix® 10 TX SoC FPGA
The Altera® Stratix® 10 TX FPGA was specifically engineered to cater to the high-speed requirements of 5G communication, cloud computing, network functions virtualization, and optical transport networks. This is made possible through the advanced PAM4 technology, which enables the high-speed FPGA device to achieve a maximum of 57.8 Gbps across 144 transceiver lanes. Additionally, the Altera® Stratix® 10 TX FPGA provides support for 28.9 Gbps NRZ and has a dual-mode modulation for backward compatibility.
| Product Name | Logic Elements (LE) | Digital Signal Processing (DSP) Blocks | Maximum Embedded Memory | Maximum User I/O Count' | Package Options |
| Altera® Stratix® 10 TX 1650 FPGA | 1679000 | 3326 | 223.5 Mb | 440 | F2397 |
| Altera® Stratix® 10 TX 2500 FPGA | 2422000 | 5011 | 208 Mb | 440 | F2397, F2912 |
| Altera® Stratix® 10 TX 2100 FPGA | 2073000 | 3960 | 239.5 Mb | 440 | F2397 |
| Altera® Stratix® 10 TX 850 FPGA | 841000 | 2016 | 72 Mb | 440 | F1760, F2397 |
| Altera® Stratix® 10 TX 400 FPGA | 378000 | 648 | 32 Mb | 392 | F1152 |
| Altera® Stratix® 10 TX 1100 FPGA | 1325000 | 2592 | 114 Mb | 440 | F1760, F2397 |
| Altera® Stratix® 10 TX 2800 FPGA | 2753000 | 5760 | 244 Mb | 440 | F2397, F2912 |
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