Altera® Cyclone® 10 GX FPGA

The Altera Cyclone 10 GX FPGA uses a column I/O structure with 12.5 Gbps transceivers located on the left-hand side of the die. The GPIOs are arranged in vertical columns with 48 I/Os per bank, each with its own high-efficiency memory controller and I/O phase-locked loop (PLL). Additionally, each GPIO bank supports LVDS pairs with a differential input and output buffers for the Altera Cyclone 10 GX FPGA, which can be configured for each pair at speeds of up to 1.4 Gbps.

Product NameLogic Elements (LE)Digital Signal Processing (DSP) BlocksMaximum Embedded MemoryMaximum User I/O Count'Package Options
Altera® Cyclone® 10 10CX105 FPGA

 

104000

1258.439 Mb284U484, F672, F780
Altera® Cyclone® 10 10CX085 FPGA8500084

 

6.473 Mb

216U484, F672
Altera® Cyclone® 10 10CX150 FPGA15000015610.652 Mb284U484, F672, F780
Altera® Cyclone® 10 10CX220 FPGA220000192

 

13.43 Mb

284U484, F672, F780