SLVS-EC RX IP is the next-generation, high-speed interface for high-resolution CMOS image sensors.

This standard is tolerant of lane-to-lane skew because of embedded clock technology that simplifies board-level design of high-speed and long-distance data transmission.

Originally developed and licensed by Sony, the SLVS-EC CMOS image sensor interface is now starting to be supported by multiple image sensor suppliers.

• Compliant with SLVS-EC Specification v1.2 and v2.0 by Sony
• Supports various functions defined by the SLVS-EC Link layer (FPGA dPCS/PMA is used as Physical layer)
• Supports Byte-to-Pixel conversion for various lane-configurations
• Supports Header analysis and Payload error detection

* The operating frequency may not be achievable depending on the speed grade, numberof lanes, and other factors of the FPGA used. Please contact Macnica sales department for information about limitations.

• Intel Cyclone V GX/SX (v1.2)
• Intel Cyclone 10 GX (v1.2 / 2.0)
• Intel Arria 10 GX/SX (v1.2 / 2.0)
• Xilinx Artix 7 (v1.2)
• Xilinx Kintex 7 (v1.2 / 2.0)
• Xilinx Kintex Ultrascale (v1.2 /2.0)
• Xilinx Kintex Ultrascale (v1.2 / 2.0)

* Please contact your local Macnica sales representative or through contact form for information about other devices.

• Encrypted RTL (Verilog HDL)
• Reference design
• Simulation environment (For ModelSim)
• User's manual, Reference manual

Resource Utilization in case of 8 LANE Full Configuration

* The above values are estimated resource utilization of the IP and Transceivers; they may vary depending on your system configuration.