V-by-One® HS IP

High-Speed Video Serial Interface Compliant with the V-by-One HS Standard

V-by-One HS is a standard for next-generation high-speed interface technology developed by THine Electronics for image and video equipment requiring higher frame rates and higher resolutions.

 

Implementing the V-by-One HS Standard Interface in Intel FPGA reduces the number of signals compared with conventional LVDS interfaces, which greatly reduces product cost.

Features

  • V-by-One HS Standard Interface achieves 4 Gbps maximum transmission rate per lane (actual rate depends on the FPGA device)
  • Supports custom video formats as well as VESA, SMPTE, and other standard formats
  • Supports flexible multi-lane designs in accordance with the user's total transmission rate requirement
  • Self-check function (FieldBET) to test connectivity between transmitter and receiver IP

Specifications

 Transmitter IPReceiver IP
Lane                                                        1~32
Pixel Data                                                       24,32,40 bit
Self Test FunctionFieldBET Pattern GeneratorFieldBET PatternChecker

Supported Devices

  • Cyclone® V GX/SX/GT/ST, Cyclone® 10 GX
  • Arria® V GX/SX/GT/ST/GZ, Arria® 10 GX/SX
  • Stratix® V GX, Stratix® 10 GX/SX (L/H-Tile)

* Please contact your local Macnica sales representative or through contact form for information about other devices.

Deliverables

  • Encrypted RTL (Verilog HDL)
  • Reference design
  • Simulation environment (For ModelSim)
  • User's manual
  • Reference design user's guide

Device Resource Utilization

IPLaneCyclone IV GXArria II GXStratix IV GX
LERegisterBlock
Memory
ALUTRegisterBlock
Memory
ALUTRegisterBlock
Memory
TX2394627820193327820193327820
RX2647749490257449490257449490
IPLaneCyclone V GXArria V GXStratix V GXArria 10 GX
LERegisterBlock
Memory
ALUTRegisterBlock
Memory
ALUTRegisterBlock
Memory
ALUTRegisterBlock
Memory
TX2159829770160329640163529590167429760
RX2227354160227453770225953510252852180

* The values in the above table are based on an example implementation. There may be some variation depending on the user’s system configuration.

Configuration Diagram

Evaluation Environment

 Product NameVendor
Main BoardArria 10 GX FPGA Development BoardIntel
Daughter CardV-by-One HS DVI FMC CardMpression

Evaluation Boards

Downloads