Multi-Rail Power Sequencer & Monitor Reference Design for Intel MAX®10 FPGA

Original Content (by Intel)

 

The Multi-Rail Power Sequencer and Monitor is a highly parameterizable set of IP blocks that can be customized to meet your power sequencing needs.  It controls the enable sequence of up to 143 output rails, can be distributed across multiple Intel® MAX® 10 devices to increase the number of monitored channels, and can draw from a mixture of Power Good (POK) inputs as well as monitored voltage rails. The sequencing can be based on voltages reaching a certain threshold as well as timed events, it offers parameterizable levels of glitch filtering on POK or voltage inputs, customizable retry responses, a comprehensive PMBus interface, and numerous other options to tailor the power sequencer to the needs of your application.

Reference Design Block Diagram

FEATURES

  • Sequence and monitor any combination of up to 144 rails
    • Up to 18 voltage-monitored rails per Intel® MAX® 10 device
    • Up to 144 digital-monitored (POK) rails per Intel® MAX® 10 device
  • Monitor overvoltage, undervoltage, and power good status
  • Easily configurable via Platform Designer GUI
  • PMBus* 1.2 compliant slave interface
  • Programmable noise filtering on analog input samples
  • Programmable debouncing (28 delay levels) of digital power good inputs
  • Latch all warning and fault conditions until cleared
  • Set defaults and dynamically control levels for overvoltage, undervoltage, and power good
  • Programmable response behavior for overvoltage and undervoltage events
  • Configurable delays between sequencing of rails, qualification window, discharge, and retries
  • Can be cascaded or instantiated multiple times within the same device as independent controllers
  • Includes simulation test bench to predict behavior

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