What's New in Quartus II Software v12.1

Altera SDK for OpenCL

Combining the OpenCL™ standard, an open royalty-free parallel programming model, with the parallel performance capability of Altera® FPGAs provides a powerful system acceleration solution. The Altera SDK for OpenCL provides a design environment for you to easily implement OpenCL applications on FPGAs. The Altera SDK for OpenCL abstracts away the complexity of FPGA design and allows FPGA designers and software programmers to program on FPGAs.

For FPGA designers, OpenCL eliminates the need to manually convert algorithms in C to HDL. Existing C code can be leveraged to automatically generate an FPGA implementation. For an overview of implementing FPGA design with OpenCL, visit Altera's OpenCL web page and read the Implementing FPGA Design with the OpenCL Standard (PDF) white paper. The Altera SDK for OpenCL is available to customers through an early access program. To discover the high performance, power-efficient acceleration that OpenCL provides with FPGAs, contact a local Altera sales representative.

DSP Builder

Altera's DSP Builder, along with MathWorks' Simulink tools, allows you to go from system definition and simulation to system implementation in a matter of minutes. DSP Builder reads Simulink model files and generates VHDL files and Tcl scripts for synthesis, hardware implementation, and simulation. It can implement high-performance Cholesky- and QR decomposition-based matrix equation solvers. To learn more, read the An Independent Analysis of Floating-Point DSP Design Flow and Performance on Altera 28 nm FPGAs (PDF) white paper – a benchmark white paper targeted on 28 nm FPGA development kits from BDTI, an independent technology analysis firm.

Here is what's new in DSP Builder v12.1:

• Improved design productivity with extended math.h primitive block coverage and support for seven different floating-point precisions, including IEEE 754 half, single, and double precisions
• Improved design reuse with new multifunction blocks that allow parameterized math functions
• Improved fast Fourier transform (FFT) implementation with improved radix-22 blockset (parameterized top-level FFT block and inverse FFT support)

DSP Builder can be purchased at $1,995 through your local Altera sales representative.

Qsys System Integration Tool

Qsys, Altera's next-generation system integration tool, saves significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. Qsys is powered by an FPGA-optimized network-on-a-chip (NoC) technology, delivering higher performance, improved design reuse, and faster verification compared to its predecessor, SOPC Builder. For more information on migrating from SOPC Builder to Qsys, refer to SOPC Builder to Qsys Migration Guidelines (PDF).

Quartus II software v12.1 includes major feature enhancements for Qsys, which include:

• Support for the ARM® AXI3 and AXI4 protocol
• 64 bit address space support

New IP Core: Interlaken

Altera's Interlaken IP core continues to scale with today's demand for more bandwidth and higher performance. Interlaken is a scalable protocol that enables chip-to-chip packet transfers at rates from 10 Gbps to 100 Gbps and above. Altera entered the market with 25G Interlaken IP cores, and now, 100G+ Interlaken IP cores are available.

For more information, please visit the Interlaken Protocol web page. New features in this release are:

• Simpler channelized interface for all 100G variants
• In-band flow control (expanded to 1, 2, 4, 8, and 16 calendar pages)
• Enhanced optional scheduler to support 100G Ethernet line rate
• Dual media access control (MAC) clocks that allow the MAC to run at 250 MHz
• Support for burst interleave mode
• Decrease round trip latency by 40 percent

New IP Core: Video Trace Monitor with Thumbnail Viewer

The new Avalon® Streaming (Avalon-ST) Video Monitor IP core extracts video packet data from selected video processing points. The new Trace System IP cores capture and display video packet data and visualize the trace data in System Console with a thumbnail viewer.

Enhanced IP Core: Deinterlacer II

• Delivers better visual quality of deinterlacing, fixing the artefacts that have been identified
• Improves edge-dependent interpolation with Sobel-based edge detection
• Fixes flashing pixels on moving objects and implements noise triggering motion detection

Transceiver Toolkit v12.1 Device Support

• Support for the Stratix V FPGA decision feedback equalization (DFE) triggered-adaptation mode which improves DFE performance significantly
• Support for Arria® V GT, Arria V GZ, and Cyclone® V device families

Stratix V FPGA Device Support

Altera's 28 nm Stratix V FPGAs deliver the industry's highest bandwidth, highest level of system integration, and ultimate flexibility with reduced cost and the lowest total power for high-end applications. This software release extends support for the Stratix V FPGA family, including programming support for all Stratix V FPGA production devices. This release also includes production support for partial reconfiguration (requires license).

Arria V and Cyclone V FPGA Device Support

The Arria V FPGA is a low-power FPGA with the ideal performance for applications requiring backplane-capable transceivers up to 12.5 Gbps. The Cyclone V FPGA is the industry's lowest power and lowest cost 28 nm FPGA. With Quartus II software v12.1, device support for both the Arria V and Cyclone V FPGA families has expanded to include:

• Full support for Arria V GZ FPGAs, including POF generation
• Advanced device support for Arria V GT FPGAs: 5AGTC3, 5AGTC7
• Advance device support for Cyclone V FPGAs: 5CGXC3 / 5CGXC4 / 5CGXC5 / 5CGTD5 / 5CEA2 / 5CEA4 / 5CEA5

Evaluate or upgrade your software with v12.1 ̶ both the Quartus II Web Edition software and ModelSim®-Altera Starter Edition simulation tool do not require a license file. The Quartus II Subscription Edition software includes a free 30-day trial, and will require a license after the 30-day period. Follow these three steps to get started:

1. Download the Quartus II software
   • Download the Quartus II Subscription Edition software (includes free 30-day trial)
   • Download the Quartus II Web Edition software (free and no license required)
2. Install the Quartus II software
3. Start evaluation/design.

Both the Subscription Edition and the free Web Edition of Quartus II software v12.1 are now available for download. Altera's software subscription program simplifies obtaining Altera design software by consolidating software products and maintenance charges into one annual subscription payment. Subscribers receive the Quartus II software, the ModelSim-Altera Starter edition and a full license to the IP Base Suite, which includes 16 of Altera's most popular IP, including digital signal processing (DSP) and memory cores. The annual software subscription is $2,995 for a node-locked PC license and is available for purchase at Altera's eStore.