Intel® Arria 10 DisplayPort 4Kp60 with Video and Image Processing Reference Design
英特爾 Arria10 DisplayPort 影像參考設計演示 DisplayPort RX 透過Bitec FMC 子卡接收影像訊號與英特爾IP所產生的測試影像作混合處理後,最後由DisplayPort TX 透過Bitec FMC 子卡輸出至螢幕最高可達 4K@60Hz 的視頻分辨率。
如上圖FPGA參考設計需要以下Module:
▼ Main Function
- DisplayPort RX core
- DisplayPort TX core
- Nios Processor
- DDR4 Memory controller
▼ Video and Image Processing IP
- Clocked Video Input II (CVI)
- Clocked Video Output II (CVO)
- Frame Buffer II
- Mixer II
▼ PHY Sub-System
- TX and RX Native PHY
- TX fPLL
- Intel® Transceiver PHY Reset Controller
- TX and RX Bitec reconfiguration module
- Transceiver reconfiguration arbiter
▼ Video PLL
▼ IOPLL 會產生3個clock
- 160 MHz : 提供DisplayPort RX Video clock source.使用
- 133 MHz : 提供DisplayPort TX Video clock source.使用
- 16 MHz :提供DisplayPort auxiliary clock.使用
▼參考設計下載如下
Hardware and Software Requirements
如果需要演示上述的參考設計 , 您需要以下硬體設備和軟件
- Hardware
- Intel Arria 10 GX FPGA Development Kit (10AX115S2F45I1SG)
- IBitec FMC daughter card revision 8, 10 or 11
https://bitec-dsp.com/product/fmc-displayport-daughter-card-revision-11/
- GPU with 4K DisplayPort source and 4K DisplayPort monitor
- DisplayPort cables
- Software
- Intel Quartus Prime Pro Edition version 17.0
Compiling the Design
請依照下面步驟進行操作
1. 由下載路徑下載 a10_dp_vip_pro.par,使用Quartus17.0 prime pro解壓縮 .par 文件後,
2. 啟動 Intel Quartus Prime Pro Edition 軟件並打開
/top.qpf。
* Note:Bitec DisplayPort FMC 子卡revision 5 及更高版本。
3. 打開 Nios II Command Shell 然後至Script folder.
- script/rerun.sh Shell script to load the FPGA hardware image (.sof) and software image(.elf).
- script/build_sw.sh Shell script to re-build the NIOS II software
View the Result
1. MSA信息告訴你DisplayPort RX已經成功接收到視頻數據, DisplayPort RX 使用 2 個通道接收 1920x1080 視頻,每通道 2700 Mbps,具有 8 bpc RGB 色度 (MISC0 = 20)。lock = 1 表示接收器接收到的視頻流是有效的視頻流。TX 使用4個通道,每通道 5400 Mbps,送出3840x2160 視頻。
參考資料
1. AN 793: Intel® Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design, intel,
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an793.pdf
2. DisplayPort Intel® FPGA IP User Guide, intel,
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_displayport.pdf